In recent years, with a trend toward a higher density and a higher degree of integration for a semiconductor integrated circuit (hereinafter, abbreviated as a “semiconductor”) chip used for electronic equipment, the number of pins of electrode terminals of a semiconductor chip has been increased and the pitch thereof has been decreased rapidly. For mounting these semiconductor chips on circuit boards, flip chip mounting is used widely in order to decrease a wiring delay.
In the flip chip mounting, solder bumps generally are formed on electrode terminals of the semiconductor chip, which then are joined to connection terminals formed on the circuit board at one time.
However, in order to mount a next-generation semiconductor chip having more than 5,000 electrode terminals on a circuit board, it is necessary to form solder bumps that correspond to a narrow pitch of 100 μm or less, but it is difficult to adapt to it with a current technique for forming solder bumps.
Moreover, since it is necessary to form a large number of solder bumps that correspond to the number of the electrode terminals, the productivity has to be raised by shortening a mounting cycle for each chip, along with the reduction in cost.
Similarly, in the semiconductor chip, the increase in the number of the electrode terminals has brought about a transition from peripheral-arranged electrode terminals to area-arranged electrode terminals.
Moreover, due to the demands for a higher density and a higher degree of integration, a limitation on a semiconductor process is expected to develop from 90 nm to 65 nm and further to 45 nm. In order to adapt to this, there is a strong demand for an insulating material having a low dielectric constant, and for the purpose of satisfying the demand, an attempt has been made so as to introduce a porous insulating material. However, in order to use a porous insulating material, mounting at a low load is required so as to alleviate the damage to the insulating material and an active circuit. Furthermore, mounting at a low load also is desired in order to prevent a semiconductor chip from being broken during handling due to the thinning of the semiconductor chip. Particularly, in the case of the area arrangement, it is necessary to constitute electrodes on an active circuit, so that there is a demand for a mounting method at a lower load.
Thus, there is a demand for a flip chip mounting method that is adaptable to a decrease in thickness and an increase in density due to the future development of the semiconductor process.
Conventionally, as a technique for forming solder bumps, plating, screen printing, and the like have been developed. The plating is suitable for a narrow pitch, but has a problem in productivity due to its complicated process. On the other hand, the screen printing has excellent productivity, but is not suitable for narrowing a pitch because of the use of a mask.
In the light of the problems described above, several techniques for forming solder bumps selectively on electrode terminals of a semiconductor chip or connection terminals on a circuit board have been developed recently. These techniques not only are suitable for forming fine solder bumps but also have excellent productivity because they can form the solder bumps all at one time, and attract attention as techniques that are adaptable to the mounting of the next-generation semiconductor chip on the circuit board.
As one of these techniques, there is the following technique: a solder paste, which is a mixture of solder powder and flux, is applied wholly onto a circuit board whose surface is provided with connection terminals, and the circuit board is heated so as to melt the solder powder, whereby solder humps are formed selectively on the connection terminals that have high wettability (see Patent Document 1, for example).
There also is a technique called a super solder method. According to this technique, a paste-like composition (chemical reaction deposition-type solder) that contains an organic acid lead salt and metallic tin as main components is applied wholly onto a circuit board on which connection terminals are formed, and the circuit board is heated so as to cause a substitution reaction between Pb and Sn, thereby depositing a Pb/Sn alloy selectively on the connection terminals of the circuit board (see Patent document 2, for example).
Conventional flip chip mounting further requires the step of injecting a resin called an underfill between the semiconductor chip and the circuit board in order to fix the semiconductor chip on the circuit board, after mounting the semiconductor chip on the circuit board on which solder bumps are formed. Because of this, there also have been problems of an increase in the number of steps and a decrease in a yield.
Then, as a method for establishing an electric connection between electrode terminals of the semiconductor chip and connection terminals of the circuit board, which are opposed to each other, and fixing the semiconductor chip onto the circuit board both at the same time, a flip chip mounting technique using an anisotropic electrically conductive material has been developed. In this technique, by supplying a thermosetting resin containing electrically conductive particles between the circuit board and the semiconductor chip, and then heating the thermosetting resin while applying a pressure to the semiconductor chip at the same time, it is possible to establish the electric connection between the semiconductor chip and the circuit board and fix the semiconductor chip to the circuit board at the same time (for example, see Patent Document 3).
However, in both of the method for forming solder bumps described in Patent Document 1 and the super solder method described in Patent Document 2, since the paste-like composition simply is supplied onto the circuit board by application, local variations in thickness and concentration occur, resulting in variations in the solder deposition amount for individual electrode terminals and connection terminals. Consequently, it is not possible to achieve solder bumps with uniform heights. Also, in these methods, since the paste-like composition is supplied by application onto the circuit board whose surface is provided with the connection terminals, namely, with projections or depressions, a sufficient amount of solder cannot be supplied onto the connection terminals serving as the projections, making it difficult to achieve a desired solder bump height necessary for the flip chip mounting.
Moreover, in the flip chip mounting method described in Patent Document 3, there are many problems in productivity and reliability that are to be solved as described below.
First, since the electric conduction between the respective terminals is obtained by mechanical contact via the electrically conductive particles, it is difficult to achieve a stable conductive state. Second, since a distance varies depending upon an amount of the electrically conductive particles that are present between the electrode terminals of the semiconductor chip and the connection terminals of the circuit board, the electric connection is unstable. Third, in order to realize the stable electric connection, crimping by pressing at a high pressure (load) is required, which is likely to break a semiconductor chip.
Patent Document 1: JP 2000-94179 A
Patent Document 2: JP 1(1989)-157796 A
Patent Document 3: JP 2000-332055 A